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16 - bit, 4 - channel/8 - channel, 250 ksps pulsar adcs data s heet AD7682 / ad7689 rev. h document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license i s granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4 700 ? 2008 C 2017 analog devices, inc. all rights reserved. technical support www.analog.com features 16- bit resolution with no missing codes 4 - channel ( AD7682 )/ 8 - channel ( ad7689 ) multiplexer with choice of inputs unipolar s ingle - e nded d ifferential (gnd sense) p seudo b ipolar throughput: 25 0 ksps inl: 0. 4 lsb typical , 1 .5 lsb m ax imum (23 ppm or fsr) dynamic range: 9 3 . 8 db sinad: 9 2 .5 db at 20 khz thd: ?1 0 0 db at 20 khz a nalog input range: 0 v to v ref with v ref up to vdd multiple reference types internal selectable 2.5 v or 4.096 v external buffered (up to 4.096 v) external (up to vdd) internal temperature sensor (temp) channel sequencer, selectable 1 - pole filter, busy indicator no pipeline delay , sar architecture single - supply 2. 3 v to 5 .5 v operation with 1.8 v to 5 .5 v logic interface serial interface compatible with spi , microwire , qspi, and dsp power dissipation 3.5 mw at 2.5 v/200 ksps 12.5 mw at 5 v/ 250 ksps standby current: 5 0 na low cost grade available 20- lead 4 mm 4 mm lfcsp package 20- lead 2.4 mm 2.4 mm wl csp pac kage applications multi channel system monitoring battery - powered equipment medical instruments : ecg /ekg mobile communications : gps power line monitoring data acquisition s eismic data acquisition systems i nstrumentation process c ontrol functional block diagram ad 768 2/ ad 768 9 ref gnd vdd vio din sck sdo cnv 1.8v to vdd 2.3v to 5.5v sequencer spi serial interface mux 16-bit sar adc band gap ref temp sensor refin in0 in1 in4 in5 in6 in7 in3 in2 com 0.5v to vdd 10f one-pole lpf 0.5v to vdd ? 0.5v 0.1f 07353-001 figure 1. general description the AD7682 / ad7689 are 4 - channel/ 8 - channel , 16- bit, charge redistribution succes si ve approximation register (sar) analog - to - digital converter s (adc s ) that operate from a single power supply, vdd. the AD7682 / ad7689 contain all components for use in a multi channel, low power dat a acquisition system , including a true 16 - bit sar adc with no missing codes; a 4 - channel ( AD7682 ) or 8 - channel ( ad7689 ) low crosstalk multiplexer that is u seful for c onfiguring the inputs as single - ended (with or without ground sense), differential , or bipolar; an internal low drift reference (selectable 2.5 v or 4.096 v) and buffer ; a temperature sensor ; a selectable one - pole filter ; and a sequencer that is useful when channels are continuously scanned in order. the AD7682 / ad7689 use a simple spi interface for writing to the configuration register and receiving conversion results . the spi interface uses a separate supply, vio , which is set to the host logic level. p ower dissipation scales with throughput. the AD7682 / ad7689 are housed in a tiny 2 0 - lead lfcsp and 20- lead wl csp with operation specified from ? 40c to +85c. table 1 . multichannel 14 - /16 - bit pulsar? adc s type channels 250 ksps 500 ksps adc driver 14 - bit 8 ad7949 ada4805 - 1 / ada4807 - 1 16 - bit 4 AD7682 ada4805 - 1 / ada4807 - 1 16 - bit 8 ad7689 ad7699 ada4805 - 1 / ada4807 - 1
AD7682/ad7689 data sheet rev. h | page 2 of 35 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision h istory ............................................................................... 2 specifications ..................................................................................... 4 timing specifications .................................................................. 7 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configurations and function desc riptions ......................... 10 typical performance characteristics ........................................... 14 terminology .................................................................................... 17 theory of operat ion ...................................................................... 18 overview ...................................................................................... 18 converter operation .................................................................. 18 transfer functions ...................................................................... 19 typical connection diagrams .................................................. 20 analog inputs .............................................................................. 21 driver amplifier choice ............................................................ 23 voltage reference output/input .............................................. 23 power supply ............................................................................... 25 supplying the adc from the reference .................................. 25 digital interface .............................................................................. 26 reading/writing during conversion, fast hosts .................. 26 reading/writing after conversion, any speed hosts .......... 26 reading/writing spanning conversion, any speed host .... 26 configuration register, cfg .................................................... 26 general timing without a busy indicator ............................. 28 general timing with a busy indicator .................................... 29 channel sequencer .................................................................... 30 read/write spanning conversion without a busy indicator ...................................................................................... 31 read/write spanning conversion with a busy indicator ..... 32 applications information .............................................................. 33 layout .......................................................................................... 33 evaluating the AD7682 / ad7689 performance ........................ 33 outline dimensions ....................................................................... 34 ordering g uide .......................................................................... 35 revision history 8 /2017 rev. g to rev. h changed cp - 20- 8 to cp - 20- 10 .................................... throughout change to product title ................................................................... 1 updated outline dimensions ....................................................... 34 changes to ordering guide .......................................................... 35 6 /2017 rev. f to rev. g change d cp - 20- 10 to cp - 20- 8 .................................... throughout changes to table 11 ........................................................................ 27 updated outline dimensions ....................................................... 34 changes to ordering guide .......................................................... 35 4 / 20 1 6 rev. e to rev. f changed ada4841 - x to ada4805 - 1 /ada4807 - 1 , table 1 ....... 1 added endnote 6, table 3 ; renumbered sequentially ................ 6 changes to figure 28 and figure 29 ............................................. 20 change s to table 10 ........................................................................ 23 changes to external reference section and the reference decoupling section ........................................................................ 24 changes to th e supplying the adc from the reference section .. 25 changes to ordering guide .......................................................... 35 1/ 20 1 5 rev . d to rev. e added wlcsp (throughout) ......................................................... 1 added wl csp signal - to - noise and sinad parameters; table 2 ................................................................................................. 3 change d ja thermal impedance (lfcsp) from 47.6c/w to 48c/w ............................................................................................... 9 added figure 6, figure 7, and table 8 ......................................... 1 2 changes to layout section ............................................................ 33 added figure 47; outline dimensions ........................................ 34 changes to ordering guide .......................................................... 35 4/ 20 12 rev. c to rev. d changes to figure 27 ...................................................................... 18 changed internal reference section to internal reference/temperature sensor section ....................................... 21 changes to internal reference/temperature sensor section ... 21 changed external reference/temperature sensor section to external reference section ........................................................... 22 changes to external reference and internal buffer section and externa l reference section ........................................................... 22 changes to ref bit, function column, table 10 ...................... 25 updated outline dimensions ....................................................... 32
data sheet AD7682/ad7689 rev. h | page 3 of 35 9/ 20 11 rev. b to rev. c changes to internal reference section ........................................ 21 changes to the external reference and internal buffer section .............................................................................................. 22 changes to the externa l reference/temperature sensor section .............................................................................................. 22 changes to table 10, ref bit description ................................... 25 6/ 20 09 rev. a to rev. b changes table 6 ................................................................................. 8 changes to figure 37 ...................................................................... 25 changes to figure 38 ...................................................................... 26 3/ 20 09 rev. 0 to rev. a changes to features section, applications section, and figure 1 ............................................................................................... 1 added table 2; renumbered sequentially ..................................... 3 changed vref to v ref ..................................................................... 4 changes to table 3 ............................................................................ 5 changes to table 4 ............................................................................ 6 changes to table 5 ............................................................................ 7 deleted endnote 2 in table 6 ........................................................... 8 changes to figure 4, figure 5, and table 7 .................................... 9 changes to figure 6, figure 9, and figure 10 .............................. 11 changes to figure 22 ...................................................................... 13 changes to overview section and converter operation section .............................................................................................. 15 changes to table 8 .......................................................................... 16 changes to figure 26 and figure 27 ............................................. 17 changes to bipolar single supply section and a nalog inputs section .............................................................................................. 18 changes to internal reference/temperature sensor section .... 20 added figure 31; renumbered sequentially ............................... 20 changes to external reference and internal buffer section and external reference section ............................................................ 21 added figure 32 and figure 33 ..................................................... 21 cha nges to power supply section ................................................. 22 changes to digital interface section , reading/writing after conversion, any speed hosts section, and configuration register, cfg section ..................................................................... 23 changes to table 10 ........................................................................ 24 added general timing without a busy indicator section and fig ure 37 ........................................................................................... 25 added general timing with a busy indicator section and figure 38 ........................................................................................... 26 added channel sequencer section and figure 39 ..................... 27 changes to read/write spanning conversion without a busy indicator section and figure 41 .................................................... 28 changes to read/write spanning conver sion with a busy indicator and figure 43 .................................................................. 29 changes to evaluating AD7682 / ad7689 p erformance section .............................................................................................. 30 added exposed pad notation to outline dimensions .............. 31 changes to ordering guide ........................................................... 31 5/ 20 08 revision 0: initial version
AD7682/ad7689 data sheet rev. h | page 4 of 35 specifications vdd = 2. 3 v to 5.5 v, vio = 1.8 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 2 . parameter test conditions/ comments ad7689 a AD7682 b / ad7689 b unit min typ max min typ max resolution 16 16 bits analog input voltage range unipolar mode 0 +v ref 0 +v ref v bipolar mode ?v ref /2 +v ref /2 ?v ref /2 +v ref /2 absolute input voltage positive input, unipolar and bipolar modes ?0.1 v ref + 0.1 ?0.1 v ref + 0.1 v negative or com input, unipolar mode ?0.1 +0.1 ?0.1 +0.1 v negative or com input, bipolar mode v ref /2 ? 0.1 v ref /2 v ref /2 + 0.1 v ref /2 ? 0.1 v ref /2 v ref /2 + 0.1 v analog input cmrr f in = 250 khz 68 68 db leakage current at 25c acquisition phase 1 1 na input impedance 1 throughput conversion rate full bandwidth 2 vdd = 4.5 v to 5.5 v 0 250 0 250 ksps vdd = 2. 3 v to 4.5 v 0 200 0 200 ksps ? bandwidth 2 vdd = 4.5 v to 5.5 v 0 6 2.5 0 6 2.5 ksps vdd = 2. 3 v to 4.5 v 0 50 0 50 ksps transient response full - scale step, full bandwidth 1.8 1.8 s full - scale step, ? bandwidth 14.5 14.5 s accuracy no missing codes 15 16 bits integral linearity error ? 4 + 4 ?1.5 0. 4 +1.5 lsb 3 differential linearity error ?1 0.25 +1.5 lsb transition noise ref = vdd = 5 v 0. 6 0.5 lsb gain error 4 ? 32 +32 ? 8 1 + 8 lsb gain error match 2 ? 4 0.5 + 4 lsb gain error temperature drift 1 1 ppm/c offset error 4 vdd = 4.5 v to 5.5 v ? 32 +32 ? 8 1 + 8 lsb vdd = 2.3 v to 4.5 v 32 5 lsb offset error match 2 ?4 0.5 +4 lsb offset error temperature drift 1 1 ppm/c power supply sensitivity vdd = 5 v 5% 1.5 1.5 lsb ac accuracy 5 dynamic range 90.5 93.8 db 6 signal -to - noise lfcsp f in = 20 khz, v ref = 5 v 90 92.5 93.5 db f in = 20 khz, v ref = 4.096 v, internal ref 89 91 92.3 db f in = 20 khz, v ref = 2.5 v, internal ref 86 87.5 88.8 db
data sheet AD7682/ad7689 rev. h | page 5 of 35 parameter test conditions/ comments ad7689 a AD7682 b / ad7689 b unit min typ max min typ max w lfcsp f in = 20 khz, v ref = 5 v 91 92 db f in = 20 khz, v ref = 4.096 v, internal ref 89.5 91 db f in = 20 khz, v ref = 2.5 v, internal ref 8 6 8 7 . 5 db sinad lfcsp f in = 20 khz, v ref = 5 v 89 91 92.5 db f in = 20 khz, v ref = 5 v, ?60 db input 30.5 33.5 db f in = 20 khz, v ref = 4.096 v internal ref 88 90 91 db f in = 20 khz, v ref = 2.5 v internal ref 86 87 88.4 db w lfcsp f in = 20 khz, v ref = 5 v 89.5 91 db f in = 20 khz, v ref = 5 v, ?60 db input 32 db f in = 20 khz, v ref = 4.096 v internal ref 88.5 89.5 db f in = 20 khz, v ref = 2.5 v internal ref 85.5 87 db total harmonic distortion (thd) f in = 20 khz ?97 ?100 db spurious - free dynamic range f in = 20 khz 105 110 db channel - to - channel crosstalk f in = 100 khz on adjacent channel(s) ?120 ?125 db sampling dynamics ?3 db input bandwidth full bandwidth 1.7 1.7 mhz ? bandwidth 0.425 0.425 mhz aperture delay vdd = 5 v 2.5 2.5 ns 1 see the analog inputs section. 2 the bandwidth is set in th e configuration register. 3 lsb means least significant bit. with the 5 v input range, one lsb is 76.3 v. 4 see the terminology section. these specifications include full temperature range variation but not the error contribution from the external refer ence. 5 with vdd = 5 v, unless otherwise noted. 6 all specificatio ns expressed in decibels are referred to a full - scale input fs r and t ested with an input signal at 0.5 db below full scale, unless otherwise specified.
AD7682/ad7689 data sheet rev. h | page 6 of 35 vdd = 2.3 v to 5.5 v, vio = 1.8 v to vdd, v ref = vdd, all specifications t min to t max , unless otherwise noted. table 3 . parameter test conditions/comments min typ max unit internal reference ref output voltage 2.5 v at 25c 2.490 2.500 2.510 v 4.096 v at 25c 4.086 4.096 4.106 v refin output voltage 1 2.5 v at 25c 1.2 v 4.096 v at 25c 2.3 v ref output current 300 a temperature drift 10 ppm/c line regulation vdd = 5 v 5% 15 ppm/v long - term drift 1000 hours 50 ppm turn - on settling time c ref = 10 f 5 ms external reference voltage range ref input 0.5 vdd + 0.3 v refin input (buffered) 0.5 vdd ? 0. 5 v current drain 2 250 ksps, ref = 5 v 50 a temperature sensor output voltage 3 25c 283 mv temperature sensitivity 1 mv/c digital inputs logic levels v il ?0.3 +0.3 vio v v ih 0.7 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format 4 pipeline delay 5 v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd 6 specified performance 2.3 5.5 v vio specified performance 1.8 vdd + 0.3 v standby current 7 , 8 vdd and vio = 5 v at 25c 50 na power dissipation vdd = 2.5 v, 100 sps throughput 1.7 w vdd = 2.5 v, 200 ksps throughput 3.5 mw vdd = 5 v, 250 ksps throughput 12.5 18 mw vdd = 5 v, 250 ksps throughput with internal reference 15.5 21 mw energy per conversion vdd = 5 v 6 0 nj temperature range 9 specified performance t min to t max ?40 +85 c 1 this is the output from the internal band gap. 2 this is an average current and scales with throughput . 3 the output voltage is internal and present on a dedicated multiplexer input. 4 unipolar mode is serial 16 - bit straight binary. bipolar mode is serial 16 - bit twos complement. 5 conversion results available immediately after completed conversion . 6 the m inimum vdd supply must be 3 v when the 2.5 v internal reference is enabled, and 4.5 v when the 4.096 v internal reference is enabled. see figure 23 for more informatio n. 7 with all digital inputs forced to vio or gnd as required. 8 during acquisition phase. 9 contact an analog devices , inc., sales representative for the extended temperature range.
data sheet AD7682/ad7689 rev. h | page 7 of 35 timing specification s vdd = 4.5 v to 5.5 v, vio = 1.8 v to vdd , all specifications t min to t max , unless otherwise noted. table 4 . parameter 1 symbol min typ max unit conversion time cnv rising edge to data available t conv 2 .2 s acquisition time t acq 1 .8 s time between conversions t cyc 4 .0 s data write/read during conversion t data 1.2 s sck period t sck t dsdo + 2 ns low time t sckl 11 ns high time t sckh 11 ns falling edge to data remains valid t hsdo 4 ns falling edge to data valid delay t dsdo vio above 2.7 v 1 8 ns vio above 2.3 v 23 ns vio above 1.8 v 28 ns cnv pulse width t cnvh 10 ns low to sdo d15 msb valid t en vio above 2.7 v 1 8 ns vio above 2.3 v 22 ns vio above 1.8 v 25 ns high or last sck falling edge to sdo high impedance t dis 32 ns low to sck rising edge t clsck 10 ns din valid setup time from sck rising edge t sdin 5 ns valid hold time from sck rising edge t hdin 5 ns 1 see figure 2 and figure 3 for load conditions.
AD7682/ad7689 data sheet rev. h | page 8 of 35 vdd = 2. 3 v to 4.5 v, vio = 1.8 v to vdd, all specifications t min to t max , unless otherwise noted. table 5 . parameter 1 symbol min typ max unit conversion time t conv 3.2 s cnv rising edge to data available acquisition time t acq 1.8 s time between conversions t cyc 5 s data write/read during conversion t data 1.2 s sck period t sck t dsdo + 2 ns low time t sckl 12 ns high time t sckh 12 ns falling edge to data remains valid t hsdo 5 ns falling edge to data valid delay t dsdo vio above 3 v 24 ns vio above 2.7 v 30 ns vio above 2.3 v 3 8 ns vio above 1.8 v 48 ns cnv t en pulse width t cnvh 10 ns low to sdo d15 msb valid vio above 3 v 21 ns vio above 2.7 v 27 ns vio above 2.3 v 35 ns vio above 1.8 v 45 ns high or last sck falling edge to sdo high impedance t dis 50 ns low to sck rising edge t clsck 10 ns din valid setup time from sck rising edge t sdin 5 ns valid hold time from sck rising edge t hdin 5 ns 1 see figure 2 and figure 3 for load conditions. i ol 500a 500a i o h 1 . 4 v to sd o c l 50 p f 07353-002 figure 2 . load circuit for digital interface timing 30% vio 70% vio 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or vio ? 0.5v 1 t delay t d e lay 1 2v if vio above 2.5v, vio ? 0.5v if vio below 2.5v. 2 0.8v if vio above 2.5v, 0.5v if vio below 2.5v. 07353-003 figure 3 . voltage levels for timing
data sheet AD7682/ad7689 rev. h | page 9 of 35 absolute maximum rat ings table 6 . parameter rating analog inputs in x , 1 com gnd ? 0.3 v to vdd + 0.3 v or vdd 130 ma ref , refin gnd ? 0.3 v to vdd + 0.3 v supply voltages vdd, vio to gnd ?0.3 v to +7 v vi o to vdd ?0.3 v to v dd + 0.3 v din, cnv, sck to gnd ?0.3 v to vio + 0.3 v sdo to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance ( lfcsp ) 48 c/w jc thermal impedance ( lfcsp ) 4.4 c/w 1 see the analog inputs section. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at thes e or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
AD7682/ad7689 data sheet rev. h | page 10 of 35 pin configuration s and function descrip tions notes 1. nc = no connect. 2. the exposed pad is not connected internally. for increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 07353-004 14 1 3 12 1 3 4 sdo 15 vio sck din 1 1 cnv vdd refin 2 ref gnd 5 gnd 7 in2 6 nc 8 nc 9 in3 10 com 19 nc 20 vdd 18 in1 17 nc 16 in0 AD7682 t o p view (not to scale) figure 4. AD7682 lfcsp pin configuration notes 1. the exposed pad is not connected internally. for increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 07353-005 14 1 3 12 1 3 4 sdo 15 vio sck din 1 1 cnv vdd refin 2 ref gnd 5 gnd 7 in5 6 in4 8 in6 9 in7 10 com 19 in3 20 vdd 18 in2 17 in1 16 in0 ad7689 t op view (not to scale) figure 5. ad7689 lf csp pin configuration table 7 . ad 7682 lfcsp and ad7689 lfcsp pin function descriptions pin no. AD7682 lfcsp mnemonic ad7689 lfcsp mnemonic type 1 description 1, 20 vdd vdd p power supply. nominally 2.5 v to 5.5 v when using an external reference and decoupled with 10 f and 100 nf capacitors. when u sing the inter nal reference for a 2.5 v output, the minimum must be 3.0 v. when using t he internal reference for 4.096 v output, the minimum must be 4. 6 v . 2 ref ref ai/o reference input/output. see the voltage reference output/input section. when the internal reference is enabled, this pin produces a selectable system reference of 2.5 v or 4.096 v. when the internal reference is disabled and the buffer is enabled, ref pr oduces a buffered version of the voltage present on the refin pin (vdd ? 0. 5 v, max imum ) , which is useful when using low cost, low power references. for improved drift performance, connect a precision reference to ref (0.5 v to vdd). for any reference meth od, this pin needs decoupling with an external 10 f capacitor connected as close to ref as possible. see the reference decoupling section. 3 refin refin ai/o internal reference output/reference buffer input. see the voltage reference output/input section. when using the internal reference, the internal unbuffered reference voltage is present and requires decoupling with a 0.1 f capacitor. when using the internal reference buffer, apply a source between 0.5 v and (vdd ? 0.5 v ) that is buffered to the ref pi n , as described in the ref pin description . 4, 5 gnd gnd p power supply ground. 6 nc in4 ai no c onnection ( AD7682 ) . analog input channel 4 ( ad7689 ). 7 in2 in5 ai analog input channel 2 ( AD7682 ) . analog input channel 5 ( ad7689 ) . 8 nc in6 ai no c onnection ( AD7682 ) . analog input channel 6 ( ad7689 ). 9 in3 in7 ai analog input channel 3 ( AD7682 ) . analog input channel 7 ( ad7689 ). 10 com com ai common channel input. all input c hannels , i n [ 7 :0] , can be referenced to a common - mode point of 0 v or v ref /2 v. 11 cnv cnv di conversion input. on the rising edge, cnv initiates the conversion. during conversion, if cnv is held low , the busy indictor is e nabled. 12 din din di data input. use this input for writing to the 14 - bit configuration register. the configuration register can be written to during and after conversion. 13 sck sck di serial data clock input. this input is used to clock out the data on s do and clock in data on din in an msb first fashion.
data sheet AD7682/ad7689 rev. h | page 11 of 35 pin no. AD7682 lfcsp mnemonic ad7689 lfcsp mnemonic type 1 description 14 sdo sdo do serial data output. the conversion result is output on this pin , synchronized to sck. in unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement. 15 vio vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). 16 in0 in0 ai analog input channel 0 . 17 nc in1 ai no c onnection ( AD7682 ) . analog input channel 1 ( ad7689 ). 18 in1 in2 ai analog input channel 1 ( AD7682 ) . analog input channel 2 ( ad7689 ). 19 nc in3 ai no c onnection ( AD7682 ) . analog input channel 3 ( ad7689 ). 21 epad epad nc exposed pad. the exposed pad is not connected internally. for increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 1 ai means a nalog i nput, ai/o means analog input/output, di means d igital input, do means d igital output, p means p ower , and nc means no internal connection.
AD7682/ad7689 data sheet rev. h | page 12 of 35 AD7682 9 8 7 6 5 4 3 2 1 nc in1 in0 vio a vdd vdd nc sdo b ref refin din sck c gnd gnd in3 cnv d nc in2 nc com e 07353-105 figure 6. AD7682 wlcsp pin configuration ad7689 9 8 7 6 5 4 3 2 1 in3 in2 in0 vio a vdd vdd in1 sdo b ref refin din sck c gnd gnd in7 cnv d in4 in5 in6 com e 07353-106 figure 7. ad7689 wlcsp pin configuration table 8 . AD7682 wlcsp and ad7689 wl csp pin function descriptions pin no. AD7682 wlcsp mnemonic ad7689 wlcsp mnemonic type 1 description b6, b8 vdd vdd p power supply. nominally 2.5 v to 5.5 v when using an external reference and decoupled with 10 f and 100 nf capacitors. when using the internal reference for a 2.5 v output, the minimum must be 3.0 v. when using the internal reference for 4.096 v output, t he minimum must be 4.6 v . c9 ref ref ai/o reference input/output. see the voltage reference output/input section. when the internal reference is enabled, this pin produces a selectable system reference of 2.5 v or 4.096 v. when the internal reference is disabled and the buffer is enabled, ref pr oduces a buffered version of the voltage present on the refin pin (vdd ? 0.5 v, maximum), which is useful when using low cost, low power references. for improved drift performance, connect a precision reference to ref (0.5 v to vdd). for any reference meth od, this pin needs decoupling with an external 10 f capacitor connected as close to ref as possible. see the reference decoupling section. c7 refin refin ai/o internal reference output/reference buffer input. see the voltage reference output/input section. when using the internal reference, the i nternal unbuffered reference voltage is present and requires decoupling with a 0.1 f capacitor. when using the internal reference buffer, apply a source between 0.5 v and (vdd ? 0.5 v) that is buffered to the ref pin, as described in the ref pin descripti on. d6, d8 gnd gnd p power supply ground. a7 nc in3 ai no connection ( AD7682 ). analog input channel 3 ( ad7689 ). e5 in2 in5 ai analog input channel 2 ( AD7682 ). analog input channel 5 ( ad7689 ). e3 nc in6 ai no connection ( AD7682 ). analog input channel 6 ( ad7689 ). d4 in3 in7 ai analog input channel 3 ( AD7682 ). analog input channel 7 ( ad7689 ). e1 com com ai common channel input. all input channels, in[7:0], can be referenced to a common - mode point of 0 v or v ref /2 v. d2 cnv cnv di conversion input. on the rising edge, cnv initiates the conversion. during conversion, if cnv is held low, the busy indictor is enabled.
data sheet AD7682/ad7689 rev. h | page 13 of 35 pin no. AD7682 wlcsp mnemonic ad7689 wlcsp mnemonic type 1 description c5 din din di data input. use this input for writing to the 14- bit configuration register. the configura - tion register can be written to during and after conversion. c3 sck sck di serial data clock input. this input is used to clock out the data on sdo and clock in data on din in an msb first fashion. b2 sdo sdo do serial data output. the conversion result is output on this pin, synchronized to sck. in unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement. a1 vio vio p input/output interface digital powe r. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). a3 in0 in0 ai analog input channel 0. b4 nc in1 ai no connection ( AD7682 ). analog input channel 1 ( ad7689 ). a5 in1 in2 ai analog input channel 1 ( AD7682 ). analog input channel 2 ( ad7689 ). e7 nc in4 ai no connection ( AD7682 ). analog input channel 4 ( ad7689 ). 1 ai means analog input, ai/o means analog input/output, di means digital input, do means digital output, p means power, and nc means no internal connection.
AD7682/ad7689 data sheet rev. h | page 14 of 35 typical performance characteristics vdd = 2.5 v to 5.5 v, v ref = 2.5 v to 5 v, vio = 2.3 v to vdd , unless otherwise noted. 1.5 1.0 0.5 0 ?0.5 ?1.5 ?1.0 inl (lsb) codes 0 16,384 32,768 49,152 65,536 inl max = +0.34 lsb inl min = ?0.44 lsb 07353-009 figure 8 . integral nonlinearity vs. code, v ref = vdd = 5 v 200k 180k 160k 140k 120k 100k 80k 60k 40k 20k 0 7ffa counts code in hex 7ffb 7ffc 7ffd 7ffe 7fff 8000 8001 8002 0 0 487 619 0 0 0 = 0.50 v ref = vdd = 5v 135,326 124,689 07353-007 figure 9 . histogram of a dc input at code center 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 50 25 75 100 125 amplitude (db of full-scale) frequency (khz) v ref = vdd = 5v f s = 250ksps f in = 19.9khz snr = 92.9db sinad = 92.4db thd = ?102db sfdr = 103db second harmonic = ?111db third harmonic = ?104db 07353-008 figure 10 . 20 khz fft, v ref = vdd = 5 v 1.5 1.0 0.5 0 ?0.5 ?1.0 0 16,384 32,768 49,152 65,536 dnl (lsb) codes dnl max = +0.20 lsb dnl min = ?0.22 lsb 07353-006 figure 11 . differential nonlinearity vs. code, v ref = vdd = 5 v 160k 140k 120k 100k 80k 60k 40k 20k 0 counts code in hex 7ffb 7ffc 7ffd 7ffe 7fff 8000 8001 8002 8003 1 78 6649 51,778 4090 60 1 = 0.78 v ref = vdd = 2.5v 63,257 135,207 07353-010 figure 12 . histogram of a dc input at code center 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 50 25 75 100 amplitude (db of full-scale) frequency (khz) v ref = vdd = 2.5v f s = 200ksps f in = 19.9khz snr = 88.0db sinad = 87.0db thd = ?89db sfdr = 89db second harmonic = ?105db third harmonic = ?90db 07353-0 1 1 figure 13 . 20 khz fft, v ref = vdd = 2.5 v
data sheet AD7682/ad7689 rev. h | page 15 of 35 100 95 90 85 80 75 70 65 60 0 50 100 150 200 snr (db) frequency (khz) v ref = vdd = 5v, ?0.5db v ref = vdd = 5v, ?10db v ref = vdd = 2.5v, ?0.5db v ref = vdd = 2.5v, ?10db 07353-041 figure 14 . snr vs. frequency 96 94 92 90 88 86 84 82 80 17.0 16.5 16.0 15.5 15.0 14.5 14.0 13.5 13.0 1.0 snr, sinad (db) enob (bits) reference voltage (v) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 s nr @ 2k h z s i nad @ 2k h z s nr @ 20k h z s i nad @ 20k h z e n o b @ 2k h z e n o b @ 20k h z 07353-013 figure 15 . snr, sinad, and enob vs . reference voltage 96 94 92 90 88 86 84 ?55 snr (db) temperature (c) ?35 ?15 5 25 45 65 85 105 125 f in = 20khz v ref = vdd = 5v v ref = vdd = 2.5v 07353-014 figure 16 . snr vs. temperature 100 95 90 85 80 75 70 65 60 0 50 100 150 200 sinad (db) frequency (khz) v ref = vdd = 5v, ?0.5db v ref = vdd = 5v, ?10db v ref = vdd = 2.5v, ?0.5db v ref = vdd = 2.5v, ?10db 07353-012 figure 17 . sinad vs. frequency 130 125 120 115 110 105 100 95 90 85 80 75 70 1.0 sfdr (db) ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 thd (db) reference voltage (v) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 sfdr = 2khz sfdr = 20khz thd = 2khz thd = 20khz 07353-016 figure 18 . sfdr and thd vs. reference voltage ?90 ?95 ?100 ?105 ?110 ?55 thd (db) temperature (c) ?35 ?15 5 25 45 65 85 105 125 f in = 20khz v ref = vdd = 5v v ref = vdd = 2.5v 07353-017 figure 19 . thd vs. temperature
AD7682/ad7689 data sheet rev. h | page 16 of 35 ?60 ?70 ?80 ?90 ?100 ?110 ?120 0 50 100 150 200 thd (db) frequency (khz) v ref = vdd = 5v, ?0.5db v ref = vdd = 2.5v, ?0.5db v ref = vdd = 2.5v, ?10db v ref = vdd = 5v, ?10db 07353-015 figure 20 . thd vs. frequency 95 94 93 92 91 90 89 88 87 86 85 ?10 snr (db) input level (db) ?8 ?6 ?2 0 ?4 f in = 20khz v ref = vdd = 5v v ref = vdd = 2.5v 07353-018 figure 21 . snr vs. input level 3 2 1 0 ?1 ?2 ?3 offset error and gain error (lsb) ?55 temperature (c) ?35 ?15 5 25 45 65 85 105 125 un i p o l ar z e r o un i p o l ar g a i n b i p o l ar z e r o b i p o l ar g a i n 07353-020 figure 22 . offset and gain errors vs. temperature 3000 2750 2500 2250 2000 1750 1500 1250 1000 100 90 80 70 60 50 40 30 20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 vdd current (a) vio current (a) vdd supply (v) 2 . 5 v i n t e rna l r e f 4 . 096 v i n t e rna l r e f i n t e rna l bu ff e r , t e m p o n i n t e rna l bu ff e r , t e m p o f f ex t e rna l r e f , t e m p o n ex t e rna l r e f , t e m p o f f v i o f s = 200ksps 07353-021 figure 23 . operating currents vs. supply 3000 2750 2500 2250 2000 1750 1500 1250 1000 180 160 140 120 100 80 60 40 20 vdd current (a) vio current (a) ?55 temperature (c) ?35 ?15 5 25 45 65 85 105 125 f s = 200ksps v dd = 5 v , i n t e rna l 4 . 096 v r e f v dd = 5 v , ex t e rna l r e f v dd = 2 . 5 , ex t e rna l r e f v i o 07353-022 figure 24 . operating currents vs. temperature sdo ca p acitive load (pf) 120 0 20 40 60 80 100 t dsdo del a y (ns) 25 20 15 10 5 0 vdd = 2.5 v , 85c vdd = 3.3 v , 25c vdd = 3.3 v , 85c vdd = 5 v , 85c vdd = 5 v , 25c vdd = 2.5 v , 25c 07353-023 figure 25 . t dsdo delay vs. sdo capacitance load and supply
data sheet AD7682/ad7689 rev. h | page 17 of 35 terminology least significant bit (lsb) the lsb is the smallest increment represented by a converter. for a n adc with n bits of resolution, the lsb expressed in volts is n ref v lsb 2 (v) = integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 27). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. offset error the first transition must occur at a level ? lsb above analog ground. the offset error is the deviation of the actual transition from that point. gain error the last transition (from 11 110 to 11111) must occur for an analog voltag e 1? lsb below the nominal full scale. the gain error is the deviation in lsb (or percentage of full - scale range) of the actual level of the last transition from the ideal level after the offset error is adjusted out. closely related is the full - scale error (also in lsb or percentage of full - scale range), which includes the effects of the offset error. aperture delay aperture delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv input and the point at which the input signal is held for a conversion. transient response transient response is the time required for the adc to accurately acquire its input after a full - scale step function is applied. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for d ynamic range is expressed in decibels. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is e xpressed in decibels. signal -to - (noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value f or sinad is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by the formula enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. channel -to - channel crosstalk channel - to - channel crosstalk is a measure of the level of crosstalk between any two adjacent channels. it is measured by applying a dc to the channel under test and applying a full - scale, 100 khz sine wave signal to the adjacent channel(s). the crosstalk is the amount of signal that leaks into the test channel , and is expressed in decibels . reference voltage temperature coefficient reference voltage temperature coefficient is derived from the typical shift of output voltage at 25c on a sample of parts at the maximum and minimum reference output voltage (v ref ) mea s ured at t min , t (25c), and t max . it is expressed in ppm/c as 6 10 ) C ( ) ( ) ( C ) ( ) c ppm/ ( = min max ref ref ref ref t t c 25 v min v max v tcv ere v ref ( max ) = maximum v ref at t min , t (25c), or t max . v ref ( min ) = minimum v ref at t min , t (25c), or t max . v ref (25 c ) = v ref at 25c. t max = +85c. t min = C 40c.
AD7682/ad7689 data sheet rev. h | page 18 of 35 theory of operation sw + msb 16 , 384 c i n x+ l sb c o mp c o n t r ol l ogi c sw i t ch es c o n t r ol bu sy o u t pu t c o d e cn v r ef g n d i n x? or c o m 4 c 2 c c c 32 , 768 c sw ? msb 16 , 384 c l sb 4 c 2 c c c 32 , 768 c 07353-026 figure 26 . adc simplified schematic overview the AD7682 / ad7689 are 4 - channel / 8 - channel , 16- bit, charge redistribution sar adc s . the se devices are capable of converting 250,000 samples per second (250 ksps) and power down between conversions. for example, w hen operating with an external reference at 1 ksps, they consume 17 w typica lly, ideal for battery - powered applications. the AD7682 / ad7689 contain all of th e components for use in a multi channel, low power da ta acquisition system , including ? 16- bit sar adc with no missing codes ? 4 - chann e l/ 8 - channel, low crosstalk multiplexer ? internal low drift reference and buffer ? temperature sensor ? selectable one - pole filter ? channel sequencer these components are configured through an spi - compatible, 14- bit register. conversion results, also spi compatible, can be read after or during conversions with the option for reading back the configuration associated with the conversion . the AD7682 / ad7689 provide the user with an on - chip track - and - hold and do not exhibit pipeline delay or latency. the AD7682 / ad7689 are specified from 2.3 v to 5.5 v and can be interfaced to any 1.8 v to 5 v digital logic family. they are housed in a 2 0 - lead , 4 mm 4 mm lfcsp a nd a 20- lead , 2.4 mm 2.4 mm wlcsp that combine space savings and allow flexible configurations. they are pin - for - pin compatible with the 16- bit ad7699 and 14 - bit ad7949 . converter operation the AD7682 / ad7689 are successive approximation adc s based on a charge redistribution dac. figure 26 shows the simplified schematic of the adc. the capacitive dac consists of tw o identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparator input are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. t he capaci tor arrays are used as sampling capacitors and acquire the analog signal on the in x + and in x ? ( or com) inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw ? open first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the in x + and in x ? ( or com) inputs captured at the end of the acquisition phase applies to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref , the co mparator input varies by binary weighted voltage steps (v ref /2, v ref /4 ...v ref /32,768). the control logic tog gles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the device returns to the acquisition phase, and the control logic generates the adc output code and a busy signal ind icator. because the AD7682 / ad7689 ha ve an on - board conversion clock, the serial clock, sck, is not required for the conversion process .
data sheet AD7682/ad7689 rev. h | page 19 of 35 transfer functions w ith the inputs config ured for unipolar range (single - ended, com with ground sense, or paired differentially with in x ? as ground sense), the data output is straight binary. with the inputs configured for bipolar range (com = v ref /2 or paired differentially with in x ? = v ref /2), the data outputs are two s complement. the ideal transfer characteristic for the AD7682 / ad7689 is shown in figure 27 and for both unipolar and bipolar ranges with the internal 4.096 v reference. 10 0 . .. 0 00 10 0 . .. 0 01 10 0 . .. 0 10 01 1 . .. 1 01 01 1 . .. 1 10 01 1 . .. 1 11 twos complement s t ra ig h t b i nar y 0 0 0 . .. 0 00 0 0 0 . .. 0 01 0 0 0 . .. 0 10 1 1 1 . .. 1 01 1 1 1 . .. 1 10 1 1 1 . .. 1 11 adc code analog input +fsr ? 1.5lsb +fsr ? 1lsb ?fsr + 1lsb ?fsr ?fsr + 0.5lsb 07353-027 figure 27 . adc ideal transfer function table 9 . output codes and ideal input voltages description unipolar analog input 1 v ref = 4.096 v digital output code ( straight binary hex) bipolar analog input 2 v ref = 4.096 v digital output code ( twos comp lement hex) fsr ? 1 lsb 4.095938 v 0xffff 3 2 . 04 7938 v 0x7fff 3 midscale + 1 lsb 2.048063 v 0x8001 62.5 v 0x0001 midscale 2.048 v 0x8000 0 v 0x0000 midscale ? 1 lsb 2.047938 v 0x7fff ? 62.5 v 0xffff ?fsr + 1 lsb 62.5 v 0x0001 ? 2. 047938 v 0x8001 ?fsr 0 v 0x0000 4 ? 2. 048 v 0x8000 4 1 w ith com or in x ? = 0 v or all inx referenced to gnd . 2 w ith com or in x ? = v ref /2. 3 this is also the code for an overranged analog input ( (in x + ) ? (in x ? ) , or com, above v ref ? gnd). 4 this is also the code for an underranged analog input ( (in x + ) ? (in x ? ) , or com, below gnd).
AD7682/ad7689 data sheet rev. h | page 20 of 35 typical connection d iagram s ad7689 ref gnd vdd vio din mosi miso ss sck sck sdo cnv 100nf 100nf 5v 10f 2 v+ v? 1.8v to vdd 0v to v ref 0v to v ref v+ v? 1 . i n t e rna l r e f e r e n c e s h o w n . s e e v o l t a g e r e f e r e n c e o u t p u t / i n p u t s e c t i o n f o r r e f e r e n c e s e l e c t i o n . n o t e s 2 . c r e f i s us u a l l y a 1 0 f c e r a m i c c a p a c i t o r ( x 5 r ) . 3 . s e e t h e d r i v e r am p l i f i e r c h o i c e s e c t i o n f o r a d d it i ona l r e c o m m en de d am p l i f i e r s . 4 . s e e t h e di g i t a l i n t e r f a c e s e c t i o n f o r c o n f i gu ri n g a n d r e a d i n g c on v e r s i o n d a t a . in0 in[7:1] com refin 100nf 0v or v ref /2 07353-028 ada4805-1/ ada4807-1 3 ada4805-1/ ada4807-1 3 figure 28 . typical application diagram with multiple supplies ref gnd vdd vio din mosi miso ss sck sck sdo cnv 100nf 100nf +5v 10f 2 v+ v? v? 1.8v to vdd v+ n o t e s 1 . i n t e rna l r e f e r e n c e s h o w n . s e e v o l t a g e r e f e r e n c e o u t p u t / i n p u t s e c t i o n f o r r e f e r e n c e s e l e c t i o n . 2 . c r e f i s us u a l l y a 1 0 f c e r a m i c c a p a c i t o r ( x 5 r ) . 3 . s e e t h e d r i v e r am p l i f i e r c h o i c e s e c t i o n f o r a d d i t i ona l r e c o m m en de d am p l i f i e r s . 4 . s e e t h e di g i t a l i n t e r f a c e s e c t i o n f o r c o n f i gu ri n g a n d r e a d i n g c on v e r s i o n d a t a . in0 in[7:1] com refin 100nf v ref /2 v ref p-p ada4805-1/ ada4807-1 3 ada4805-1/ ada4807-1 3 ad7689 07353-029 figure 29 . typical applicati on diagram using bipolar input
data sheet AD7682/ad7689 rev. h | page 21 of 35 unipolar or bipolar figure 28 shows an example of the recommended connection diagram f or the AD7682 / ad7689 when multiple supplies are available. bipolar single supply figure 29 shows an example of a system with a bipolar input using single supplies with the internal reference (optional different vio supply). this circuit is also useful when the amplifier/signal cond itioning circuit is remotely located with some common mode present. note that for any input config - ur ation, the in x inputs are unipolar and are always referenced to gnd (no negative voltages even in bipolar range) . for this circuit, a rail - to - rail input/o utput amplifier can be used ; however, take the offset voltage vs. input common - mode range into consideration (1 lsb = 62.5 v with v ref = 4.096 v ). note that the conversion results are in two s complement format when using the bipolar input configuration. refer to the an - 581 application note , biasing and decoupling op amps in single supply applications, for additional details about using single - supply amplifiers. analog inputs input structure figure 30 shows an equivalent circuit of the input structure of the AD7682 / ad768 9 . the two diodes, d1 and d2, provide esd protection for the analog inputs, in[7:0] and com. care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 v because this causes the diodes to become forward bias ed and to start conducting current. these diodes can handle a maximum forward - biased current of 130 ma. for instance, these conditions may eventual ly occur when the input buffer supplies are different from vdd. in such a case, for example, an input buffer with a short circuit, the current limitation can be used to protect the device . c i n r i n d1 d2 c pin inx+ or inx? or com gnd vdd 07353-030 figure 30 . equivalent analog input circuit th is analog input structure allows the sampling of the true differential signal between in x + and com or i n x + and in x ? . (com or in x ? = gnd 0.1 v or v ref 0.1 v). by using these differential inputs, signals common to both inputs are rejected , as shown in figure 31. 70 65 60 55 50 45 40 35 30 1 10k 10 cmrr (db) 100 1k frequency (khz) 07353-031 figure 31 . analog i nput cmrr vs. frequency during the acquisition phase, the impedance of the analog i nputs can be modeled as a parallel combination of the capacito r, cpin, and the network formed by the series connection of rin and cin. cpin is primarily the pin capacitance. rin is typically 2.2 k? and is a lumped component comp osed of serial res istors and the on resistance of the switches. cin is typically 27 pf and is mainly the adc sampling capacitor. selectable low - pass filter during the conversion phase, when the switches are opened, the input impedance is limited to c pin . while the AD7682 / ad7689 are acquiring, r in and c in make a one - pole, low - pass filter that reduces undesirable aliasing effects and limits the noise from the driving circuitry. the low - p ass filter can be programmed for the full bandwidth or ? of the bandwidth with cfg[6] , as shown in table 11. this setting changes r in to 19 k?. note that the converter through p ut must also be reduced by ? when using the filter. if the max imum throughput is used with th e bandwidth ( bw ) set to ? , the converter acquisition time, t acq , is violated, result ing in increased thd.
AD7682/ad7689 data sheet rev. h | page 22 of 35 input configurations figure 32 shows the different methods for configuring the analog inputs with the configuration register , cfg[ 1 2:10 ]. refer to the configuration register, cfg section for more details. the analog inputs can be configured as shown in ? figure 32 ( a ) , single - ended referenced to system ground; cfg[12:10] = 111 2 . in this configuration, all inputs ( in[7:0] ) have a range of gnd to v ref . ? figure 32 ( b ) , bipolar differential wit h a common reference point; com = v ref /2; cfg[12:10] = 010 2 . unipolar differential with com connected to a ground sense; cfg[12:10] = 110 2 . in this configuration, all inputs in[7:0] have a range of gnd to v ref . ? figure 32 ( c ) , bipolar differential pairs with the negative input channel referenced to v ref /2; cfg[12:10] = 00x 2 . unipolar differential pairs with the negative input channel referenced to a ground sense; cfg[12 :10] = 10x 2 . in these configurations, the positive input channel s have the range of gnd to v ref . the negative input channel s are a sense referred to v ref /2 for bipolar pairs , or gnd for unipolar pairs . the positive channel is configured with cfg[9:7]. if cfg[9:7] is even, then in 0 , in 2 , in 4 , and in 6 are used. if cfg[9:7] is odd, then in 1 , in 3 , in 5 , and in 7 are used , as indicated by the channels with parentheses in figure 32 ( c ) . for example, for in0/ in 1 pairs with the positive channel on in0, cfg[9:7] = 000 2 . for in 4 / in 5 pairs with the positive channel on in 5 , cfg[9:7] = 1 01 2 . note that for the sequencer, detail ed in the channel sequencer section, the positive channels are always in 0 , in 2 , in 4 , and in 6 . ? figure 32 ( d ) , inputs configured in any of the preceding combinations (showing that the AD7682 / ad7689 can be configured dynamically). g n d c o m ch 0 + ch 3 + ch 1 + ch 2 + ch 4 + ch 5 + ch 6 + ch 7 + ch 0 + ch 3 + ch 1 + ch 2 + ch 4 + ch 5 + ch 6 + ch 7 + c o m? g n d c o m i n 1 i n 0 i n 2 i n 3 i n 4 i n 5 i n 6 i n 7 i n 1 i n 0 i n 2 i n 3 i n 4 i n 5 i n 6 i n 7 i n 1 i n 0 i n 2 i n 3 i n 4 i n 5 i n 6 i n 7 i n 1 i n 0 i n 2 i n 3 i n 4 i n 5 i n 6 i n 7 a ? 8 chann e l s, s i n g l e e nd ed b ? 8 chann e l s, c o mm o n r e f e rnc e g n d c o m ch 0 + (?) ch 1 + (?) ch 2 + (?) ch 3 + (?) ch 0 ? (+) ch 1 ? (+) ch 0 + (?) ch 1 + (?) ch 0 ? (+) ch 1 ? (+) ch 2 ? (+) ch 3 ? (+) c ? 4 chann e l s, d i ff e r e n t i al g n d c o m ch 2 + ch 3 + ch 4 + ch 5 + d ? c o m b i na t io n c o m? 07353-032 figure 32 . multiplexed analog input configurations seq ue ncer the AD7682 / ad7689 include a channel sequencer useful for scanning channels in a repeated fashion . refer to the channel sequencer sec tion for further details on the sequencer operation. source resistance when the source impedance of the driving circuit is low, the AD7682 / ad7689 can be driven directly. large source imped - ances significantly affect the ac performance, especially thd. the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency .
data sheet AD7682/ad7689 rev. h | page 23 of 35 driver amplifier choice although the AD7682/ ad7689 are easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and transition noise performance of the AD7682 / ad7689 . note that the AD7682/ ad7689 have a noise much lower than most other 16-bit adcs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. the noise from the amplifier is filtered by the AD7682 / ad7689 analog input circuit low-pass filter made by r in and c in , or by an external filter, if one is used. because the typical noise of the AD7682/ ad7689 is 35 v rms (with v ref = 5 v), the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 )( 2 35 35 log20 n 3db loss nef snr where: f C3db is the input bandwidth in megahertz of the AD7682/ ad7689 (1.7 mhz in full bw or 425 khz in ? bw), or the cutoff frequency of an input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver must have a thd performance commensurate with the AD7682/ ad7689. figure 20 shows thd vs. frequency for the AD7682 / ad7689. ? for multichannel, multiplexed applications on each input or input pair, the driver amplifier and the AD7682 / ad7689 analog input circuit must settle a full-scale step onto the capacitor array at a 16-bit level (0.0015%). in amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. this may differ significantly from the settling time at a 16-bit level and must be verified prior to driver selection. table 10. recommended driver amplifiers amplifier typical application ada4805-1 low noise, small size, and low power ada4807-1 very low noise and high frequency ada4627-1 precision, low noise, and low input bias ada4522-1 precision, zero drift, and emi enhanced ada4500-2 precision, rail-to-rail in put/output, and zero input crossover distortion voltage reference output/input the AD7682 / ad7689 allow the choice of a very low temper- ature drift internal voltage reference, an external reference, or an external buffered reference. the internal reference of the AD7682/ ad7689 provide excel- lent performance and can be used in almost all applications. there are six possible choices of voltage reference schemes, briefly described in table 11, with more details in each of the following sections. internal reference/temperature sensor the precision internal reference, suitable for most applications, can be set for either a 2.5 v or a 4.096 v output, as detailed in table 11. with the internal reference enabled, the band gap voltage is also present on the refin pin, which requires an external 0.1 f capacitor. because the current output of refin is limited, it can be used as a source if followed by a suitable buffer, such as the ad8605 . note that the voltage of refin changes depending on the 2.5 v or 4.096 v internal reference. enabling the reference also enables the internal temperature sensor, which measures the internal temperature of the AD7682 / ad7689 , and is therefore useful for performing a system calibration. for applications requiring the use of the temperature sensor, the internal reference must be active (internal buffer can be disabled in this case). note that, when using the temperature sensor, the output is straight binary referenced from the AD7682/ ad7689 gnd pin. the internal reference is temperature compensated to within 10 mv. the reference is trimmed to provide a typical drift of 10 ppm/c. connect the AD7682/ ad7689 as shown in figure 33 for either a 2.5 v or 4.096 v internal reference. ref gnd temp AD7682/ ad7689 10f 100nf refin 07353-049 figure 33. 2.5 v or 4.096 v internal reference connection
AD7682/ad7689 data sheet rev. h | page 24 of 35 external reference and internal buffer for improved dr ift performance , an external reference can be used with the internal buffer , as shown in figure 34 . the external source is connected to ref in , the input to the on - chip unity - gain buffer, and the output is produced on the ref pin. a n external ref erence can be used with the internal buffer w ith or without the temperature sensor enabled. refer to table 11 for register details. wit h the buffer enabled, the gain i s unity and is limited to an input/output of vdd = ? 0.2 v ; however, the maximum voltage allowable must be ( vdd ? 0.5 v ) . the internal reference buffer is useful in multiconverter appli ca tions because a buffer is typically required in these applications. in addition , a low power reference can be used because the internal buffer provides the necessary performance to drive the sar architecture of the AD7682 / ad7689 . ref gnd temp AD7682/ ad7689 10 f 100nf refin ref source (vdd C 0.5v) 07353-132 figure 34 . external reference using interna l buffer external reference in any of the six voltage reference schemes , an external ref - erence can be connected directly on the ref pin as shown in figure 35 because the output impedance of ref is > 5 k . to reduce power consumption, power down the reference and buffer . refer to table 11 for register details. for improved drift performance, an ext ernal reference from the family of devices tha t includes the adr43 0 , adr431 , adr433 , adr434 , a nd adr435 , or the family of devices that includes the adr440 , adr441 , adr443 , adr444 , and adr445 is recommend ed. ref gnd temp 10f refin ref source 0.5v < ref < (vdd + 0.3v) no connection required AD7682/ ad7689 07353-047 figure 35 .external reference note that the best snr is achieved with a 5 v external reference as the internal refer e nce is limited to 4.096 v. the snr degradation is as follows : 5 096 . 4 log 20 loss snr reference decoupling whether using an internal or external reference, the AD7682 / ad7689 voltage reference output/ input , ref , has a dynamic input impedance and must be driven by a low impedance source with efficient decoupling between the ref and gnd pins. this decoupling depends on the choice of the voltage reference but usually consists of a low esr capacitor connected to ref and gnd with minimum parasitic inductance. a 10 f (x5r, 1206 size) ceramic chip capacitor is appropriate when using th e internal reference , a member of the adr430 , adr431 , adr433 , adr434 , a nd adr435 family of e xternal references , a member of the adr440 , adr441 , adr443 , adr444 , and adr445 family of e xternal reference s , or a low impedance buffer such as the ad8031 or the ad8605 . the placement of the reference decoupling capacitor is also importan t to the performance of the AD7682 / ad7689 , as explained in the layout section. mount t he decoupling capacitor with a thick pcb trace on the same side as the adc at the ref pin . the gn d must also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias. if desired, smaller reference decoupling capacitor values down to 2.2 f can be used with a minimal impact on performance, especially on dnl. regardless, there is no need for an additional lower value ceramic decoupl ing capacitor ( for example, 100 nf) between the ref and gnd pins. for applications that use multiple AD7682 / ad7689 device s or other pulsar devices, it is more effective to use the internal reference buffer to buffer the external reference voltage , thus reducing sar conversion crosstalk . the voltage reference temperature coefficient (tc) directly impacts full scale; therefore, in applications where full - scale accuracy matters, care must be taken with the tc. for instance, a 1 0 ppm/c t c of the reference changes full scale by 1 lsb/c.
data sheet AD7682/ad7689 rev. h | page 25 of 35 power supply the AD7682 / ad7689 use two power supply pins : an analog and digital core supply ( vdd ) , and a digital input/output inter - face supply ( vio ) . vio allows direct interface with any logic between 1.8 v and vdd. to reduce the supplies needed, the vio and vdd pins can be tied together. the AD7682 / ad7689 are independent of power supply sequencing between vio and vdd. additionally, they are very insensitive to power supply variations over a wide frequency range , as shown in figure 36. 75 70 65 60 55 50 45 40 35 30 1 10k 10 pssr (db) 100 1k frequency (khz) 07353-034 figure 36 . psrr vs. frequency the AD7682 / ad7689 power down automatically at the end of each c onversion phase ; therefore, the operating currents and power scale linearly with the sampling rate . this makes the device ideal for low sampling rate s (even of a few hertz) , and low battery - powered applications. 10,000 1000 100 10 1 0.1 0.010 0.001 10 1m 100 operating current (a) 1k 10k 100k sampling rate (sps) vdd = 5v, internal ref vdd = 5v, external ref vdd = 2.5v, external ref vio 07353-040 figure 37 . operating c urrents vs. sampl ing rate supplying the adc fr om the reference for simplified applications, the AD7682 / ad7689 , with their low operating current, can be supplied directly using an external reference circuit like the one shown in figure 38. the reference line can be driven by ? t he system power supply directly . ? a reference voltage with enough current output capability, such as the adr430 , adr431 , adr433 , adr434 , adr435 , adr440 , adr441 , adr443 , adr444 , or adr445 . ? a reference buffer, such as the ad8605 , which can also filter the system power supply, as shown in figure 38. ad 860 5 ad 768 9 vio ref vdd 10f 1f 0.1f 10 ? n? 5v 5v 5v 1f 1 1 optional reference bufferand filter. 0.1f 07353-035 figure 38 . example of an application circuit
AD7682/ad7689 data sheet rev. h | page 26 of 35 digital interface the AD7682 / ad7689 use a simple 4 - wire interface and are compatible with spi, microwire?, qspi ? , digital hosts, and dsps ( for example, blackfin? adsp - bf53x , sharc ? , adsp - 219x , and adsp - 218x ) . the interface uses the cnv, din, sck, and sdo signals and allows cnv, which initiates the conversion, to be independent of the readback timing. this is useful in low jitter sampling or simultaneous sampling applications. a 14- bi t register, cfg[13:0], is used to configure the adc for the channel to be converted, the reference selection, and other components, which are detailed in the configuration register, cfg section. when cnv is low , r eading/ w r i ting can occur during conversion, acquisition, and spanning conversion (acquisition plus conversion). the cfg word is updated on the first 14 sck rising e dges , and c o nver sion results are output on the first 15 (or 16 , if busy mode is selected) sck falling edges. if the cfg readback is enabled, an additional 14 sck falling edges are required to output the cfg word associated with the con - version results with the cfg msb following the lsb of the conversion result. a discontinuous sck is recommended because the device is selected with cnv low , and sck activity begin s to write a new configuration word and clock out data. the timing diagrams indicate digital activity (sck, cnv, din, and sdo) during the conversion. however, due to the possibility of performance degradation, digital activity occur s only prior to the safe data reading/writing time, t data , because the AD7682 / ad7689 provide error correction circuitry that can correct for an incorrect bit during this time. from t data to t conv , there is no error co rrect ion , and conversion results may be corrupted. c onfigure the AD7682 / ad7689 and initiate the busy indicator (if desired) prior to t data . it is also possible to corrupt the sample by having sck or din transitions near the sampling instant. therefore, it is recommended to keep the digital pins quiet for approximately 2 0 ns before and 10 ns after the rising edge of cnv, using a discontin uous sck whenever possible to avoid any potential performance degradation. reading/ writing during conversion , fast hosts when reading / writing during conversion (n) , conversion results are for the previous (n ? 1) conversion , and w riting the cfg register is for the next (n + 1) acquisition and conversion. after the cnv is brought high to initiate conversion, it must be brought low again to allow reading/writing during conversion . r eading/writing must only occur up to t data and , because this time is limited, the host must use a fast sck . the sck frequency required is calculated by data sck t edges sck number f _ _ reading / writing after conversion , any speed hosts when reading/writing after conversion, or during acquisition (n), conversion results are for the previous (n ? 1) conversion , and writing is for the (n + 1) acquisition. for the maximum throughput, the only time restricti on is that the reading/writing take place during the t acq (min imum ) time. for slow throughputs, the time restriction is dictated by the throughput required by the user, and the host is free to run at any speed. thus for slow hosts, data access must take pl ace during the acquisition phase. reading/writing spanning conversion , any speed host when reading/writing spanning conversion, the data access starts at the current acquisition (n) and spans into the con - version (n) . conversion results are for the previo u s (n ? 1) conversion , and writing the cfg register is for the next (n + 1) acquisition and conversion. similar to reading/writing during conversion , reading/writing must only occur up to t data . for the maximum throughput, the only time restriction is that reading/writing take place during the t acq + t data time. for slow throughputs, the time restriction is dictated by the required throughput , and the host is free to run at any speed. similar to reading/writing during acquisition, for slow hosts, the data a ccess must take place during the acquisition phase with additional time into the conversion. d ata access spanning conver sion requires the cnv to be driven high to initiate a new conversion , and data access is not allowed when cnv is high. th erefore , the ho st must perform two bursts of data access when using this method. configuration regist er , cfg the AD7682 / ad7689 use a 14 - bit configuration register (cfg[13:0]) , as detailed in table 11, to configur e the input s, the channel to be converted, the one - pole filter bandwidth, the reference, and the channel sequencer. the cfg register is latched (msb first) on din with 14 sck rising edges . the cfg update is edge depende nt , allowing for asynchronous or synchronous hosts.
data sheet AD7682/ad7689 rev. h | page 27 of 35 the register can be written to during conversion, during acquisition, or spanning acquisition/conversion , and is updated at the end of conversion, t conv (max imum ). there is always a one deep delay when writing the cfg register. at power - up, the cfg register is undefined and two dummy conversions are required to update the register. to preload the cfg register with a factory setting, hold din high for two con versions ( cfg[13:0] = 0 x3fff ) . this sets the AD7682 / ad7689 for the following: ? in[7:0] unipolar referenced to gnd, sequenced in order . ? full bandwidth for a one - pole filter . ? internal reference/temp erature sensor disabled, buffer enabled . ? enables the internal sequencer . ? no read back of the cfg register. table 11 summarizes the configuration regist er bit details. see the theory of operation section for more details . 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cfg incc incc incc in x in x in x bw ref ref ref seq seq rb table 11 . configuration register description bit (s) name description [ 13 ] cfg configuration u pdate . 0 = keep current configuration settings. 1 = overwrite contents of register. [ 12:10 ] incc input c hannel c onfiguration . selection of pseudo bipolar , pseudo differential , pairs , single - ended , or temperature sensor. refer to the input configurations section. bit 12 bit 11 bit 10 function 0 0 x 1 bipolar differential pairs; inx? referenced to v ref /2 0.1 v. 0 1 0 bipolar; inx referenced to com = v ref /2 0.1 v. 0 1 1 temperature sensor. 1 0 x 1 unipolar differential pairs; inx? referenced to gnd 0.1 v. 1 1 0 unipolar, in x referenced to com = gnd 0.1 v. 1 1 1 unipolar, in x referenced to gnd. [ 9:7 ] inx input c hannel s election in b inary f ashion . AD7682 ad7689 bit 9 bit 8 bit 7 channel bit 9 bit 8 bit 7 channel 1 0 0 in0 0 0 0 in0 1 0 1 in1 0 0 1 in1 1 1 0 in2 1 1 1 in3 1 1 1 in7 6 bw select b andwidth for low -p ass f ilter . refer to the selectable low - pass filter section. 0 = of bw, uses an additional series resistor to further bandwidth limit the noise. maximum throughput must be reduced to . 1 = full bw. 5:3 ref reference/b uffer s election . selection of internal, external, external buffered , and enabling of the on - chip temperature sensor. refer to the voltage reference output/input section. bit 5 bit 4 bit 3 function 0 0 0 internal reference and temperature sensor enabled. ref = 2.5 v buffered output. 0 0 1 internal reference and temperature sensor enabled. ref = 4.096 v buffered output. 0 1 0 use external reference. temperature sensor enabled. internal buffer disabled. 0 1 1 use external reference. internal buffer and temperature sensor enabled. 1 0 0 do not use. 1 0 1 do not use. 1 1 0 use external reference. internal reference, internal buffer, and temperature sensor disabled. 1 1 1 use external reference. internal buffer enabled. internal reference and temperature sensor disabled. [ 2:1 ] seq channel s equencer . allows for scanning channels in an in0 to in [7:0] fashion. refer to the channel sequencer section. bit 2 bit 1 function 0 0 disable sequencer. 0 1 update configuration during sequence. 1 0 scan in0 to in [7:0] (set in cfg[9:7]), then temperature. 1 1 scan in0 to in[7:0] (set in cfg[9:7]). [0] rb read back the cfg r egister . 0 = read back current configuration at end of data. 1 = do not read back contents of configuration. 1 x means dont care.
AD7682/ad7689 data sheet rev. h | page 28 of 35 general timing witho ut a busy indicator figure 39 details the timing for all three modes : read/writ e duri ng conversion (rdc) , read/write after conversion (rac) , and read/write spanning conversion (rsc) . note that the gating item for both cfg an d data readback is at the end of conversion (eoc). at eoc, if cnv is high, the busy indicator is disabled. as detaile d in the digital interface section , the data access must occur up to safe data reading/writing time, t data . if the full cfg word is not written to prior to eoc, it is discarded and the current configuration remain s . if the conversion result is not read out fully prior to eoc, it is lost as the adc updates sdo with the msb of the current conversion . for detailed timing, refer to figure 42 and figure 43, which depict reading/ writing spanning conversion with all timing details , including setup, h old, and sck. when cnv is brought low after eoc, sdo is driven from high impedance to the msb. falling sck edges clock out bits starting with m sb ? 1 . the sck can idle high or low depending on the clock polarity ( cpol ) and clock phase ( cpha ) settings if spi is used. a simple solution is to use cpol = cpha = 0 as shown in figure 39 with sck idling low . from power - up, i n any read/write mode, the first thre e conver - sion results are undefined because a valid cfg does not take place until the second eoc ; therefore, two dummy conversions are required. if the state machine writes the cfg during the power - up state (rdc shown), the cfg register must be rewritten a t the next phase . the first valid data occurs in p hase (n + 1) when the cfg register is written during p hase (n ? 1) . acquisition (n ? 1) undefined acquisition (n) acquisition (n + 1) acquisition (n + 2) phase power up eoc eoc soc eoc eoc conversion (n ? 1) undefined conversion (n) conversion (n + 1) conversion (n ? 2) undefined t conv t cyc t data cnv cnv cnv din sdo xxx msb xxx msb xxx notes 1. cnv must be high prior to the end of conversion (eoc) to avoid the busy indicator. 2. a total of 16 sck falling edges are required to return sdo to high-z. if cfg readback is enabled, a total of 30 sck falling edges is required to return sdo to high-z. data (n) data (n ? 1) xxx data (n ? 1) xxx data (n ? 1) xxx data (n ? 1) xxx data (n ? 2) xxx data (n ? 2) xxx data (n ? 2) xxx data (n ? 2) xxx data (n ? 3) xxx din sdo data (n + 1) data (n) data (n) data (n) data (n + 1) din cfg (n) cfg (n) cfg (n + 2) cfg (n + 2) cfg (n + 1) cfg (n + 1) cfg (n + 3) sdo sck 1 16 16 16 16 note 2 note 2 1 1 1 sck 1 16 16 16 n n n n n + 1 n + 1 n + 1 1 1 sck 1 1 1 16 16 16 1 1 cfg (n) cfg (n + 1) cfg (n + 2) rdc rac rsc cfg (n) cfg (n + 1) cfg (n + 2) cfg (n + 3) note 2 note 1 note 1 note 1 07353-043 figure 39 . general interface timing for the AD7682 / ad7689 without a busy indicator
data sheet AD7682/ad7689 rev. h | page 29 of 35 general timing w ith a busy indicator figure 40 details the t iming for all three modes: rdc , rac , and rsc . note that the gating item for both cfg and data readback is at eoc . the data access must occur up to safe data reading/writing time, t data . if the full cfg word is not written to prior to eoc, it is discarded and the current configuration remains. at the eoc, if cnv is lo w, the busy indicator enables . in addition, to generate the busy indicator properly, the host must assert a mi nimum of 17 sck falling edges to return sdo to high impedance because the last bit on sdo remains active. unlike the case detailed in the read/write spanning conversion without a busy indicator section, if the conversion result is not read out fully prior to eoc, the last bit clocked out remains. if this bit is low, the busy signal indicator cannot be generated because the busy generation requires either a high impedanc e or a remaining bit high - to - low transition. a good example of this occurs when an spi host sends 16 scks because these are usually limited to 8 - bit or 16 - bit bursts; therefore, the lsb remains. because the transition noise of the AD7682 / ad7689 is 4 lsbs peak - to - peak (or grea ter), the lsb is low 50% of the time. for this interface, the spi host needs to burst 24 scks, or a qspi interface ca n be used and programmed for 17 scks. the sck can idle high or low depending on the cpol and cpha settings if spi is used. a simple solutio n is to use cpol = cpha = 1 (not shown) with sck idling high. from power - up, in any read/write mode, the first three conver - sion results are undefined because a valid cfg does not take place until the second eoc ; thus , two dummy conversions are required. a lso, if the state machine writes the cfg during the power - up state (rdc shown), the cfg register need s to be rewritten again at the next phase. the first valid data occurs in p hase (n + 1) when the cfg register is written during phase (n ? 1). acquisition (n ? 1) undefined acquisition (n) acquisition (n + 1) acquisition (n + 2) phase power up eoc eoc start of conversion (soc) eoc eoc conversion (n) conversion (n + 1) conversion (n ? 2) undefined t conv t cyc t data cnv cnv cnv din rdc rac rsc sdo notes 1. cnv must be low prior to the end of conversion (eoc) to generate the busy indicator. 2. a total of 17 sck falling edges are required to return sdo to high-z. if cfg readback is enabled, a total of 31 sck falling edges is required to return sdo to high-z. din sdo data (n + 1) data (n) data (n) data (n) data (n + 1) din cfg (n) cfg (n + 2) cfg (n + 1) cfg (n + 3) sdo sck 1 1 1 1 sck 1 n n + 1 17 17 17 17 17 17 17 17 1 n n + 1 17 1 n n + 1 17 sck 1 1 1 1 1 xxx note 1 note 1 note 1 note 2 note 2 note 2 cfg (n) cfg (n + 1) cfg (n + 2) cfg (n) cfg (n + 1) cfg (n + 2) cfg (n + 3) conversion (n ? 1) undefined 07353-044 figure 40 . general interface timing for the AD7682 / ad7689 with a busy indicator
AD7682/ad7689 data sheet rev. h | page 30 of 35 channel sequencer the AD7682 / ad7689 include a channel sequencer useful for scanning ch annels in a repeated fashion . channels are scanned as singles or pairs, with or without the temperature sensor, after the last channel is sequenced. the sequencer starts with in0 and finishes with in[7:0] set in cfg[9:7]. for paired channels, the channels are paired depend - ing on the last channel set in cfg[9:7]. note that in sequencer mode, the channel s are always paired with the positive input on the even channels ( i n 0 , in 2 , in 4 , and in 6 ) , and with the negative input on the odd channels ( in 1 , in 3 , in 5 , and in 7 ) . for example , setting cfg[9:7] = 110 or 111 scan s all pairs with the positive input s dedicated to in 0 , in 2 , in 4 , and in 6 . cfg[2:1] are used to enable the sequencer. after the cfg register is updated, din must be held low while reading data out for bit 13, or the cfg register begins updating again. note that w hile operating in a sequence, some bits of the cfg register can be changed. however, if changing cfg[11] (paired or single channel) or cfg[9:7] (last channel in sequence), the sequence reinitializes and converts in0 (or in0/in1 pair s ) after the cfg register is updated. figure 41 details the timing for all three modes without a b usy indicator . refer to the read/write spanning conversion without a busy indicator section and the read/write spanning conversion without a busy indicator section for more details. the sequencer can also be used with the b usy indicator and details for these timings can be found in the general timing with a busy indicator section and the read/write spanning conversion with a busy indicator section . for sequencer operatio n, the cfg register must be set during the (n ? 1) phase after power - up. on p hase (n), the sequencer setting takes place and acquires in0. the first valid conversion result is available at p hase (n + 1). after the last channel set in cfg[9:7] is converted, the internal temp erature sensor data is output (if enabled) , followed by acquisition of in0. examples with a ll channels configured for unipolar mode to gnd , including the internal temperature sensor, the sequence scan s in the following order : in0, in1, in2, in3, in4, in5, in6, in7, temp, in0, in1, in2 for paired channels with the internal temperature sensor enabled, the sequencer scan s in the following order : i n0, in2, in4, in6, temp, in0 note that in1, in3, in5, and in7 are referenced to a gnd sense or v ref /2 , as detailed in the input configurations section . acquisition (n ? 1) undefined acquisition (n), in0 acquisition (n + 1), in1 acquisition (n + 2), in2 phase power up eoc eoc soc eoc eoc conversion (n ? 1) undefined conversion (n), in0 conversion (n + 1), in1 conversion (n ? 2) undefined t conv t cyc t data cnv cnv cnv din sdo xxx msb xxx msb xxx notes 1. cnv must be high prior to the end of conversion (eoc) to avoid the busy indicator. 2. a total of 16 sck falling edges are required to return sdo to high-z. if cfg readback is enabled, a total of 30 sck falling edges is required to return sdo to high-z. data in0 data (n ? 1) xxx data (n ? 1) xxx data (n ? 1) xxx data (n ? 1) xxx data (n ? 2) xxx data (n ? 2) xxx data (n ? 2) xxx data (n ? 2) xxx data (n ? 3) xxx din sdo data in1 data in0 data in0 data in0 data in1 din cfg (n) cfg (n) sdo sck 1 note 1 16 16 16 16 note 2 note 2 note 2 2 1 1 1 sck 1 16 16 16 n n n n n + 1 n + 1 n + 1 1 1 sck 1 1 1 16 16 16 1 1 cfg (n) rdc rac rsc cfg (n) 07353-046 figure 41 . general channel sequencer timing without a busy indicator
data sheet AD7682/ad7689 rev. h | page 31 of 35 read/write spanning conversion without a busy indicator this mode is used when the AD7682/ ad7689 are connected to any host using an spi, serial port, or fpga. the connection diagram is shown in figure 42, and the corresponding timing is given in figure 43. for the spi, the host must use cpha = cpol = 0. reading/writing spanning conversion is shown, which covers all three modes detailed in the digital interface section. for this mode, the host must generate the data transfer based on the conversion time. for an interrupt driven transfer that uses a busy indicator, refer to the read/write spanning conversion with a busy indicator section. a rising edge on cnv initiates a conversion, forces sdo to high impedance, and ignores data present on din. after a conversion initiates, it continues until completion, irrespective of the state of cnv. cnv must be returned high before the safe data transfer time (t data ), and held high beyond the conversion time (t conv ) to avoid generation of the busy signal indicator. after the conversion is complete, the AD7682/ ad7689 enter the acquisition phase and power-down. when the host brings cnv low after t conv (maximum), the msb enables on sdo. the host also must enable the msb of the cfg register at this time (if necessary) to begin the cfg update. while cnv is low, both a cfg update and a data readback take place. the first 14 sck rising edges are used to update the cfg, and the first 15 sck falling edges clock out the conversion results starting with msb ? 1. the restriction for both configuring and reading is that they both must occur before the t data time of the next conversion elapses. all 14 bits of cfg[13:0] must be written or they are ignored. in addition, if the 16-bit conversion result is not read back before t data elapses, it is lost. the sdo data is valid on both sck edges. although the rising edge can capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 16 th (or 30 th ) sck falling edge, or when cnv goes high (whichever occurs first), sdo returns to high impedance. if cfg readback is enabled, the cfg register associated with the conversion result is read back msb first following the lsb of the conversion result. a total of 30 sck falling edges is required to return sdo to high impedance if this is enabled. miso mosi sck ss cnv for spi use cpha = 0, cpol = 0. sck sdo din AD7682/ ad7689 digital host 07353-036 figure 42. connection diagram for the AD7682 / ad7689 without a busy indicator update (n) cfg/sdo update (n + 1) cfg/sdo acquisition (n) acquisition (n - 1) msb 1 2 begin data (n ? 1) begin cfg (n + 1) cfg msb 14 15 see note see note notes 1. the lsb is for conversion results or the configuration register cfg (n ? 1) if 15 sck falling edges = lsb of conversion results. 29 sck falling edges = lsb of configuration register. on the 16th or 30th sck falling edge, sdo is driven to high impendance. 16/ 30 conversion (n) end data (n ? 1) end cfg (n + 1) cfg lsb x x > t conv lsb sck cnv din sdo 14 15 16/ 30 conversion (n ? 1) end data (n ? 2) end cfg (n) cfg lsb x x t conv t data t cnvh t data t dis t dis t en t dsdo t hsdo t hdin t sdin t clsck t en t en t sck t sckh t sckl t dis t dis t conv lsb t acq t cyc (quiet time) (quiet time) eoc eoc return cnv high for no busy return cnv high for no busy 07353-037 figure 43. serial interface timing for the AD7682 / ad7689 without a busy indicator
AD7682/ad7689 data sheet rev. h | page 32 of 35 read/write spanning conver s ion w ith a busy indicator this mode is used when the AD7682 / ad7689 are connected to any host using an spi, serial port , or fpga with an interrupt input . the connection diagram is shown in figure 44 , and the corres pon ding timing is given in figure 45. for the spi, the host must use cpha = cpol = 1. reading/writing spanning con - version is shown , which covers all three modes detailed in the digital interface section. a rising edge on cnv initiates a conversion, ignores data present on din , and forces sdo to high impedance. after the conversion initiates , it continues until completion , irrespective of the state of cnv. cnv must be returned low bef ore the safe data transfer time ( t data ), and then held low b eyond the conversion time ( t conv ) to generat e the busy signal indicator. when the conversion is comp lete, sdo transitions from high i mpedance to low (data ready) , and with a pull - up t o vio, sdo can be used to interrupt the host to begin data transfer. after the conversion is complete, the AD7682 / ad7689 enter the acquisition phase and power - down. the host must enable the msb of the cfg register at this time (if necessary) to begin the cfg update. while cnv is low , both a cfg update and a da ta read back take place. the first 14 sck rising edges are used to update the cfg register , and the first 1 6 sck falling edges clock out the conversion results starting with the msb. the restriction for both configuring and reading is that they both occur b efore the t data time elapses for the next conversion. all 14 bits of cfg[13:0] must be written or they are ignored. i f the 16- bit conversion result is not read back before t data elapses, it is lost. the sdo data is valid on both sck edges. although the ris ing edge c an c apture the data, a digital host using the sck falling edge allow s a faster reading rate, provided it has an acceptable hold time. after the optional 1 7 th (or 31 st ) sck falling edge , sdo returns to high impedance. i f the optional sck falling edge is not used, the busy feature cannot be detected , as described i n the general timing with a busy indicator section . i f cfg readback is enabled, the cfg register associated with the conversion result is read back msb first following the lsb of the conversion result. a total of 3 1 sck falling edges is required to return sdo to high impedance if this is enabled. AD7682/ ad7689 miso mosi sck ss sdo vio for spi use cph a = 1, cpo l = 1. sck cnv din digital host irq 07353-038 figure 44 . connection diagram for the AD7682 / ad7689 with a busy indicator sck acquisition (n) acquisition (n + 1) cnv din sdo msb msb ? 1 1 2 begin data (n ? 1) beign cfg (n + 1) cfg msb lsb + 1 lsb 15 15 see note see note notes: 1. the lsb is for conversion results or the configuration register cfg (n ? 1) if 16 sck falling edges = lsb of conversion results. 30 sck falling edges = lsb of configuration register. on the 17th or 31st sck falling edge, sdo is driven to high impendance. otherwise, the lsb remains active until the busy indicator is driven low. 16 16 17/ 31 17/ 31 conversion (n) conversion (n ? 1) (quiet time) end data (n ? 2) end data (n ? 1) end cfg (n + 1) end cfg (n) x x x x x x t data update (n + 1) cfg/sdo lsb + 1 lsb conversion (n ? 1) (quiet time) update (n) cfg/sdo t cyc t acq t hdin t hsdo t dsdo t sdin t data t conv t cnvh t dis t dis t dis t en t en t en cfg msb ?1 t sck t sckh t sckl 07353-039 figure 45 . serial interface timing for the AD7682 / ad7689 with a busy indicator
data sheet AD7682/ad7689 rev. h | page 33 of 35 application s information layout the printed circuit board ( pcb) that houses the AD7682 / ad7689 must be designed so that the analog an d digital sections are separate d and confined to certai n areas of the board. the pin configuration of the AD7682 / ad7689 , with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7682 / ad7689 is used as a shield. fast switching signals, such as cnv or clocks, must not run near analog signal paths. avoid c rossover of d igital and analog signals. use at least one ground plane. it c an be common or split between the digital and analo g sections. in the latter case, join the planes underneath the AD7682 / ad7689 . the AD7682 / ad7689 voltage reference input, ref, has a dynamic input impedance and must be decoupled with minimal parasitic inductances. this is achieved by placing the reference decoupl ing ceramic capacitor close to ( ideally , right up against) the ref and gnd pins and connecting them with wide, low impe dance traces. finally, the power supplies of the AD7682 / ad7689 (vdd and vio) must be decoupled with ce ramic capacitors, typically 100 nf, placed close to the AD7682 / ad7689 , and connected using short , wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. the an - 617 application note has informat ion on pcb layout and assembly. this information is particularly important for guiding customers who do not hav e experience with wlcsp. evaluating the AD7682 / ad7689 performance other recommended layouts for the AD7682 / ad7689 are outlined in the documentation of the evaluation board for the AD7682 / ad7689 ( e va l - ad76 8 2 ed z / e va l - ad7689 ed z ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the c onverter and e valuation d evelopment data capture board , e va l - c ed1z .
AD7682/ad7689 data sheet rev. h | page 34 of 35 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant t o jedec standards mo-220-wggd-11. 4.10 4.00 sq 3.90 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 2.65 2.50 sq 2.35 1 20 6 10 1 1 15 16 5 bot t om view t o p view side view for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 02-21-2017-b exposed pad pkg-003578 se a ting plane pin 1 indic a t or area options (see detail a) detail a (jedec 95) figure 46 . 20 - lead lead frame chip scale package [ lfcsp ] 4 mm 4 mm body and 0.75 mm package height (cp - 20 - 10 ) dimensions shown in millimeters a b c d e 2.430 2.390 sq 2.350 1 2 3 4 5 6 7 8 9 bot t om view (bal l side up) t o p view (bal l side down) bal l a1 identifier 0.560 0.500 0.440 0.330 0.300 0.270 side view 0.230 0.200 0.170 0.300 0.260 0.220 0.50 ref 0.50 ref 0.25 ref 0.433 ref coplanarity 0.05 se a ting plane 05-13-2014- a pkg-004466 figure 47 . 20 - ball wafer level chip scale package [ wlcsp ] (c b - 20 - 12) dimensions shown in millimeters
data sheet AD7682/ad7689 rev. h | page 35 of 35 ordering guide model 1 , 2 integral nonlinearity no missing code temperature range package description package option ordering quantity AD7682bcpz 2 lsb max 16 bits ?40c to +85c 20- lead lfcsp cp -20-10 tray, 490 AD7682bcpzrl7 2 lsb max 16 bits ?40c to +85c 20- lead lfcsp cp -20-10 reel, 1,500 AD7682bcbz -rl7 2 lsb max 16 bits ?40c to +85c 20- ball wlcsp cb -20-12 reel, 1,500 ad7689acpz 6 lsb max 15 bits ?40c to +85c 20- lead lfcsp cp -20-10 tray, 490 ad7689acpzrl7 6 lsb max 15 bits ?40c to +85c 20- lead lfcsp cp -20-10 reel, 1,500 ad7689bcpz 2 lsb max 16 bits ?40c to +85c 20- lead lfcsp cp -20-10 tray, 490 ad7689bcpzrl7 2 lsb max 16 bits ?40c to +85c 20- lead lfcsp cp -20-10 reel, 1,500 ad7689bcbz -rl7 2 lsb max 16 bits ?40c to +85c 20- ball wlcsp cb -20-12 reel, 1,500 eval - AD7682edz evaluation board eval - ad7689edz evaluation board eval - ced1z converter evaluation and development board 1 z = rohs complaint part. 2 the eval - ced1z controller board allows a pc to control and communicate with all analog devices evaluation boards whose model numbers e nd in ed. ? 2008 C 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07353 - 0 - 8/17(h)

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